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Clock Jitter limit on resolution.

  • The 75 MHz clock signal at CTF was measured for it's clock jitter using a spectrum analyser with a phase noise measurement function.
  • This figure was calculated as 1.8 ps.
  • However, the internal clock will be used due to time limitations on setting up this clock signal.

  • The signal to noise ratio of a sine wave sampled with a known clock jitter is given by:
$SNR_{Jitter}[dBc]=-20\log_{10}\left ( 2\pi f_{IN}t_{Jitter} \right )$

  • $f_{IN}$ is the frequency of the wave and $t_{Jitter}$ is the clock jitter.

Struck SIS3320-250 8 Channel 250 MHz 12-bit ADC/Digitizer

-- JackTowler - 27 May 2014

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Topic revision: r4 - 12 Jan 2015 - JackTowler

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